Intel is working to significantly increase the cache of its processors
Intel Director of Component Development Mike Mayberry announced that his division is currently working on the implementation of a new type of floating-body cell, which should allow Intel processors to be equipped with much larger cache memory in the future.
Currently, SRAM (static RAM) is used for these purposes, but the density of its chips is not too high today – six transistors are required to store one bit of information. An alternative technology, EDRAM (embedded RAM) is too expensive to manufacture and, moreover, does not have sufficient speed indicators.
To store a bit of information when using a floating-body cell, only one transistor is required.
Recall that this is not the first development that uses this effect – almost two years ago, Toshiba announced the development of floating-body DRAM.
The originality of Intel’s approach lies in the fact that its design uses two gates instead of one, together with a varying thickness of the oxide substrate to change the strength of the charge entering the memory cell and logic transistor.
In this regard, I recall Intel’s developments aimed at creating three-gate transistors, which the company intends to implement in the next 3-7 years.